Field isolation regions are used in integrated circuit memory arrays to isolate memory cells from each other. EPROMS (erasable and programmable memories) are a type of CMOS transistor array that requires field isolation. Most EPROMs being manufactured today have single-transistor memory cells. The transistor has a double-poly gate structure, or "stack", in which an upper poly forms the control gate and wordlines and a lower poly form a floating gate. Field oxide (FOX) regions are used to provide capacitive coupling between these gates, as well as to isolate adjacent cells.
FIG. 1 illustrates the FOX regions of a portion of a conventional EPROM or EEPROM array. In conventional fabrication, the source lines are implanted after the formation of the FOX regions and the gate "stack". After the stack etching, the implant is performed such that the implants are self-aligned to the stack and the field oxide edges. The FOX regions form an array of "islands", each designed to have a sideways "H" shape. Cells having this pattern of FOX regions are sometimes referred to as "H cells". They are also sometimes referred to as "T cells" because the active areas are T-shaped.
Despite the straight-edged design of the FOX regions, after fabrication, their actual shape resembles a "dog bone", as illustrated by the dotted lines The field oxide corners are rounded instead of square. This rounding occurs as a result of limitations of photolithography optical resolution and a different oxidation rate at the corner areas.
The rounded ends of the FOX regions have undesirable effects, well known in the art of semiconductor fabrication. For example, if misalignment occurs between the field oxide regions and transistor gates, the channel widths of two adjacent transistors across the source line may differ, and the channel widths may vary across the length of each transistor. If cells in two adjacent rows share a source line, as is the case in some memory array layouts such as flash EEPROMs having a "double poly" structure, the capacitive coupling ratio between the control gate and floating gate may vary from cell to cell across the source line. The result is unequal programming and erase characteristics.
A need exists for a CMOS memory array structure and a method of fabricating it that avoids undesired effects of field oxide corner rounding.